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14-Bit, 80 MSPS, A/D Converter AD9444
FEATURES
80 MSPS guaranteed sampling rate 100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz 73.1 dB SNR with 70 MHz input 97 dBc SFDR with 70 MHz input Excellent linearity DNL = 0.4 LSB typical INL = 0.6 LSB typical 1.2 W power dissipation 3.3 V and 5 V supply operation 2.0 V p-p differential full-scale input LVDS outputs (ANSI-644 compatible) Data format select Output clock available
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2 DRGND DRVDD DFS DCS MODE BUFFER VIN+ VIN- T/H PIPELINE ADC 14 CMOS OR LVDS OUTPUT STAGING 2 28 D13-D0 2 DCO REF
05089-001
AD9444
OUTPUT MODE OR
CLK+ CLK-
CLOCK AND TIMING MANAGEMENT
VREF SENSE REFT REFB
Figure 1.
APPLICATIONS
Multicarrier, multimode cellular receivers Antenna array positioning Power amplifier linearization Broadband wireless Radar, infared imaging Communications instrumentation
Optional features allow users to implement various selectable operating conditions, including data format select and output data mode. The AD9444 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (-40C to +85C).
PRODUCT HIGHLIGHTS
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The AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit and is optimized for power, small size, and ease of use. The product operates at up to an 80 MSPS conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.
2. Ease of use: On-chip reference and track-and-hold. An output clock simplifies data capture. 3. Packaged in a Pb-free, 100-lead TQFP/EP. 4. Clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.
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Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
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GENERAL DESCRIPTION
1. High performance: Outstanding SFDR performance for multicarrier, multimode 3G and 4G cellular base station receivers.
AD9444 TABLE OF CONTENTS
DC Specifications ............................................................................. 3 AC Specifications.............................................................................. 4 Digital Specifications........................................................................ 5 Switching Specifications .................................................................. 6 Explanation of Test Levels........................................................... 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Definitions of Specifications ........................................................... 9 Pin Configurations and Function Descriptions ......................... 10 Equivalent Circuits ......................................................................... 14 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 20 Analog Input and Reference Overview ................................... 20 Clock Input Considerations...................................................... 22 Power Considerations................................................................ 23 Digital Outputs ........................................................................... 23 Timing ......................................................................................... 23 Operational Mode Selection ..................................................... 23 Evaluation Board ........................................................................ 24 LVDS Evaluation Board Schematics ........................................ 25 LVDS Mode Evaluation Board Bill of Materials (BOM) ...... 30 CMOS Evaluation Board Schematics ...................................... 32 CMOS Mode Evaluation Board Bill of Materials (BOM)..... 37 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 39
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9444 DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = -0.5 dBFS, DCS on, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error VOLTAGE REFERENCE Output Voltage1 Load Regulation @ 1.0 mA Reference Input Current (External 1.0 V Reference) INPUT REFERRED NOISE ANALOG INPUT Input Span Input Common-Mode Voltage Input Resistance3 Input Capacitance3 POWER SUPPLIES Supply Voltage AVDD1 AVDD2 DRVDD--LVDS Outputs DRVDD--CMOS Outputs Supply Current AVDD1 AVDD22 IDRVDD2--LVDS Outputs IDRVDD2--CMOS Outputs PSRR Offset Gain POWER CONSUMPTION DC Input--LVDS Outputs DC Input--CMOS Outputs Sine Wave Input2--LVDS Outputs Sine Wave Input2--CMOS Outputs Temp Full Full Full Full Full 25C Full Full Full Full Full Full 25C Full Full Full Full Test Level VI VI VI VI VI I VI V V VI V VI V V V V V 0.87 Min AD9444BSVZ-80 Typ Max 14 Guaranteed 0.3 0.4 0.4 0.6 Unit Bits
6 -3.0 -0.8 -1.3 -1.7
6 +3.0 +0.8 +1.3 +1.7
mV % FSR LSB LSB LSB V/C %FS/C
12 0.002 1.0 2 80 1.0 2 3.5 1 2.5 1.13 125
V mV A LSB rms V p-p V k pF
Full Full Full Full Full Full Full Full Full Full Full Full Full Full
IV IV IV IV VI VI VI V V V VI V VI V
3.14 4.75 3.0 3.0
3.3 5.0 3.3 217 71 55 12 1 0.2 1.21 1.07 1.25 1.11
3.46 5.25 3.6 3.6 240 80 62
V V V V mA mA mA mA mV/V %/V
1.4
W W W W
1 2
The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444. Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 differential termination on each pair of output bits for LVDS output mode and approximately 5 pF loading on each output bit for CMOS output mode. 3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
Rev. 0 | Page 3 of 40
AD9444 AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed reference (1.0 V mode), AIN = -0.5 dBFS, DCS on, unless otherwise noted. Table 2.
Parameter SIGNAL-TO-NOISE-RATIO (SNR) fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz SIGNAL-TO-NOISE-AND DISTORTION (SINAD) fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz WORST HARMONIC, SECOND OR THIRD fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz WORST SPUR EXCLUDING SECOND OR HARMONICS fIN = 10 MHz fIN = 35 MHz fIN = 70 MHz fIN = 100 MHz TWO-TONE SFDR fIN = 10.8 MHz @ -7 dBFS, 9.8 MHz @ -7 dBFS fIN = 70.3 MHz @ -7 dBFS, 69.3 MHz @ -7 dBFS ANALOG BANDWIDTH Temp 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full 25C 25C 25C 25C 25C 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full 25C 25C 25C Full Test Level IV IV I IV IV IV V IV IV I IV IV IV V V V V V IV IV I IV IV IV V IV IV I IV IV IV V IV IV I IV IV IV V V V V 91 87 91 87 90 87 Min 73.0 72.7 72.4 72.3 72.3 72.0 AD9444BSVZ-80 Typ Max 74.0 73.7 73.1 72.3 73.0 72.7 72.4 72.2 72.2 72.0 74.0 73.7 73.1 72.3 12.1 12.0 11.9 11.8 97 97 97 96 -97 -97 -97 -96 -102 -103 -102 -99 -102 -100 650 -93 -93 -93 -93 -93 -93 -91 -87 -91 -87 -90 -87 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBFS dBFS MHz
Rev. 0 | Page 4 of 40
AD9444 DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 k, unless otherwise noted. Table 3.
Parameter CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUT BITS--CMOS Mode (D0 to D13, OTR)1 DRVDD = 3.3 V High Level Output Voltage Low Level Output Voltage DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR) VOD Differential Output Voltage2 VOS Output Offset Voltage CLOCK INPUTS (CLK+, CLK-) Differential Input Voltage Common-Mode Voltage Differential Input Resistance Differential Input Capacitance Temp Full Full Full Full Full Test Level IV IV VI VI V Min 2.0 0.8 +200 +10 2 AD9444BSVZ-80 Typ Max Unit V V A A pF
-10
Full Full Full Full Full Full Full Full
IV IV VI VI IV VI V V
3.25 0.2 247 1.125 0.2 1.3 8 545 1.375
V V mV V V V k pF
1.5 10 4
1.6 12
1 2
Output voltage levels measured with 5 pF load on each output. LVDS RTERM = 100 .
Rev. 0 | Page 5 of 40
AD9444 SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted. Table 4.
Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse Width High1 (tCLKH) CLK Pulse Width Low1 (tCLKL) DATA OUTPUT PARAMETERS Output Propagation Delay--CMOS (tPD)2 (DX, DCO+) Output Propagation Delay--LVDS (tPD)3 (DX+, DCO+) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Temp Full Full Full Full Full Full Full Full Full Full Test Level VI V V V V IV VI V V V AD9444BSVZ-80 Min Typ Max 80 10 12.5 4 4 3 3 5.25 5 12 0.2 8 7.5 Unit MSPS MSPS ns ns ns ns ns Cycles ns ps rms
1 2
With duty cycle stabilizer (DCS) enabled. Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load. 3 LVDS RTERM = 100 . Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N-1 AIN
N N+1
tCLKL tCLKH
1/fS CLK+ CLK-
tPD
DATA OUT N-12 N-11 12 CLOCK CYCLES DCO+ DCO-
05089-002
N
N+1
tCPD
Figure 2. LVDS Mode Timing Diagram
Rev. 0 | Page 6 of 40
AD9444
N-1 N N+1 VIN
tCLKL tCLKH
CLK-
N+2
CLK+
tPD
12 CYCLES
DX
N-12
N-11
N-1
N
tDCOPD
DCO+ DCO-
05089-003
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level I II III IV V VI Definitions 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 7 of 40
AD9444 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter ELECTRICAL AVDD1 AGND AVDD2 AGND DRVDD DGND AGND DGND AVDD1 DRVDD AVDD2 DRVDD AVDD2 AVDD1 D0 to D13 DGND CLK, MODE AGND VIN+, VIN- AGND VREF AGND SENSE AGND REFT, REFB AGND ENVIRONMENTAL Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature With Respect to Min -0.3 -0.3 -0.3 -0.3 -4 -4 -4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -65 -40 Max +4 +6 +4 +0.3 +4 +6 +6 DRVDD + 0.3 AVDD1 + 0.3 AVDD2 + 0.3 AVDD1 + 0.3 AVDD1 + 0.3 AVDD1 + 0.3 +125 +85 300 150 Unit V V V V V V V V V V V V V C C C C
Thermal Resistance
The heat sink of the AD9444 package must be soldered to ground. Table 6.
Package Type 100-Lead TQFP/EP JA 19.8 JB 8.3 JC 2 Unit C/W
Typical JA = 19.8C/W (heat-sink soldered) for multilayer board in still air. Typical JB = 8.3C/W (heat-sink soldered) for multilayer board in still air. Typical JC = 2C/W (junction to exposed heat sink) represents the thermal resistance through heat-sink path. Airflow increases heat dissipation effectively reducing JA. Also, more metal directly in contact with the package leads, from metal traces, through holes, ground, and power planes, reduces the JA. It is required that the exposed heat sink be soldered to the ground plane.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 40
AD9444 DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes must be present over all operating ranges. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Offset Error The major carry transition should occur for an analog value 1/2 LSB below VIN+ = VIN-. Offset error is defined as the deviation of the actual transition from that point. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Power-Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Signal-to-Noise and Distortion (SINAD) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full scale). Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product.
ENOB =
(SINAD - 1.76 )
6.02
Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSBs beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Maximum Conversion Rate The clock rate at which parametric testing is performed.
Rev. 0 | Page 9 of 40
AD9444 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 DCS MODE 98 AVDD1 89 AVDD1 82 DRGND 83 DRVDD 95 AVDD1 94 AVDD1 93 AVDD1 92 AVDD1 90 AVDD1 87 AVDD1 81 D13+ (MSB) 91 AVDD1
99 AGND
97 AGND
96 AGND
88 AGND
86 AGND
79 D12+
80 D13-
77 D11+
78 D12-
76 D11-
75 DRVDD 74 DRGND 73 D10+ 72 D10- 71 D9+ 70 D9- 69 D8+ 68 D8- 67 DRGND 66 D7+ 65 D7- 64 DCO+ 63 DCO- 62 DRVDD 61 DRGND 60 D6+ 59 D6- 58 D5+ 57 D5- 56 D4+ 55 D4- 54 DRVDD 53 DRGND 52 D3+ 51 D3-
85 OR+
AVDD1 DNC DNC DNC OUTPUT MODE DFS LVDSBIAS AVDD1 AVDD1
1 2 3 4 5 6 7 8 9
SENSE 10 VREF 11 AGND 12 REFT 13 REFB 14 AGND 15 AVDD1 16 AVDD1 17 AVDD1 18 AVDD2 19 AGND 20 VIN+ 21 VIN- 22 AGND 23 AVDD1 24 AVDD1 25
AD9444
TOP VIEW (Not to Scale)
AVDD2 31 AGND 32
84 OR-
AVDD2 28 AVDD2 29
C1 33 AVDD1 34
CLK- 37 AVDD1 38 AVDD2 39
AVDD1 35 CLK+ 36
AVDD2 40 AVDD1 41
AVDD1 42 (LSB) D0- 43 D0+ 44
D1- 45 D1+ 46 DRVDD 47
AVDD1 26 AVDD1 27
AVDD2 30
DRGND 48
D2- 49 D2+ 50
DNC = DO NOT CONNECT
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. 0 | Page 10 of 40
05089-004
AD9444
Table 7. Pin Function Descriptions--100-Lead TQFP/EP in LVDS Mode
Pin No. 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98 2 to 4 5 Mnemonic AVDD1 Description 3.3 V (5%) Analog Supply. Pin No. 44 45 46 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 49 50 51 52 55 56 57 58 59 60 63 64 65 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85 100 Mnemonic D0+ D1- D1+ DRVDD DRGND D2- D2+ D3- D3+ D4- D4+ D5- D5+ D6- D6+ DCO- DCO+ D7- D7+ D8- D8+ D9- D9+ D10- D10+ D11- D11+ D12- D12+ D13- D13+ (MSB) OR- OR+ DCS MODE Description D0 True Output Bit. D1 Complement Output Bit. D1 True Output Bit. 3.3 V Digital Output Supply (3.0 V to 3.6 V). Digital Ground. D2 Complement Output Bit. D2 True Output Bit. D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. Data Clock Output--Complement. Data Clock Output--True. D7 Complement Output Bit. D7 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit. D10 True Output Bit. D11 Complement Output Bit. D11 True Output Bit. D12 Complement Output Bit. D12 True Output Bit. D13 Complement Output. D13 True Output Bit. Out-of-Range Complement Output Bit. Out-of-Range True Output Bit. Clock Duty Cycle Stabilizer (DCS) Control Pin, CMOS-Compatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS.
DNC OUTPUT MODE
6
DFS
7
LVDSBIAS
10
SENSE
11
VREF
12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink 13
AGND
Do Not Connect. These pins should float. CMOS Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs. Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement, DFS = low (ground) for offset binary format. Set Pin for LVDS Output Current. Place 3.7 k resistor terminated to DRGND. Reference Mode Selection. Connect to AGND for internal 1 V reference, and connect to AVDD2 for external reference. 1.0 V Reference I/O--Function Dependent on SENSE. Decouple to ground with 0.1 F and 10 F capacitors. Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND. Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 14) with 0.1 F and 10 F capacitors. Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 13) with 0.1 F and 10 F capacitors. 5.0 V Analog Supply (5%). Analog Input--True. Analog Input--Complement. Internal Bypass Node. Connect a 0.1 F capacitor from this pin to AGND. Clock Input--True. Clock Input--Complement. D0 Complement Output Bit (LVDS Levels).
REFT
14
REFB
19, 28 to 31, 39 to 40 21 22 33
AVDD2 VIN+ VIN- C1
36 37 43
CLK+ CLK- D0- (LSB)
Rev. 0 | Page 11 of 40
AD9444
100 DCS MODE 99 AGND 84 D13 (MSB) 98 AVDD1 97 AGND 89 AVDD1 88 AGND 82 DRGND 83 DRVDD 95 AVDD1 94 AVDD1 93 AVDD1 92 AVDD1 91 AVDD1 90 AVDD1 87 AVDD1 96 AGND 86 AGND 81 D12 80 D11 79 D10 85 OR 78 D9 77 D8 76 D7
75 DRVDD 74 DRGND 73 D6 72 D5 71 D4 70 D3 69 D2 68 D1 67 DRGND 66 D0 (LSB) 65 DNC 64 DCO+ 63 DCO- 62 DRVDD 61 DRGND 60 DNC 59 DNC 58 DNC 57 DNC 56 DNC 55 DNC 54 DRVDD 53 DRGND 52 DNC 51 DNC
AVDD1 DNC DNC DNC OUTPUT MODE DFS DNC AVDD1 AVDD1
1 2 3 4 5 6 7 8 9
SENSE 10 VREF 11 AGND 12 REFT 13 REFB 14 AGND 15 AVDD1 16 AVDD1 17 AVDD1 18 AVDD2 19 AGND 20 VIN+ 21 VIN- 22 AGND 23 AVDD1 24 AVDD1 25
AD9444
TOP VIEW (Not to Scale)
AVDD2 31 AGND 32
AVDD2 28 AVDD2 29
C1 33 AVDD1 34 AVDD1 35
CLK+ 36 CLK- 37
AVDD1 38 AVDD2 39
AVDD2 40 AVDD1 41
DNC 45 DNC 46 DRVDD 47
AVDD1 26 AVDD1 27
AVDD2 30
DRGND 48
AVDD1 42
DNC 49 DNC 50
DNC 43 DNC 44
DNC = DO NOT CONNECT
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. 0 | Page 12 of 40
05089-005
AD9444
Table 8. Pin Function Descriptions--100-Lead TQFP/EP in CMOS Mode
Pin No. 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98 2 to 4, 7, 43 to 46, 49 to 52, 55 to 60, 65 5 Mnemonic AVDD1 Description 3.3 V (5%) Analog Supply. Pin No. 33 Mnemonic C1 Description Internal Bypass Node. Connect a 0.1 F capacitor from this pin to AGND. Clock Input--True. Clock Input--Complement. 3.3 V Digital Output Supply (2.5V to 3.6 V). Digital Ground. Data Clock Output-- Complement (CMOS Levels). Data Clock Output-- True. D0 Output Bit (LSB) (CMOS Levels). D1 Output Bit. D2 Output Bit. D3 Output Bit. D4 Output Bit. D5 Output Bit. D6 Output Bit. D7 Output Bit. D8 Output Bit. D9 Output Bit. D10 Output Bit. D11 Output Bit. D12 Output Bit. D13 Output Bit. Out-of-Range Output. Clock Duty Cycle Stabilizer (DCS) Control Pin, CMOSCompatible. DCS = low (AGND) to enable DCS (recommended). DCS = high (AVDD1) to disable DCS.
DNC
Do Not Connect. These pins should float. CMOS Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode, and OUTPUT MODE = 1 (AVDD1) for LVDS outputs. Data Format Select Pin. CMOS control pin that determines the format of the output data. DFS = high (AVDD1) for twos complement, DFS = low (ground) for offset binary format. Reference Mode Selection. Connect to AGND for internal 1 V reference, and connect to AVDD2 for external reference. 1.0 V Reference I/O-- Function Dependent on SENSE. Decouple to ground with 0.1 F and 10 F capacitors. Analog Ground. The exposed heat sink on the bottom of the package must be connected to AGND. Differential Reference Output. Decoupled to ground with 0.1 F capacitor and to REFB (Pin 14) with 0.1 F and 10 F capacitors. Differential Reference Output. Decoupled to ground with a 0.1 F capacitor and to REFT (Pin 13) with 0.1 F and 10 F capacitors. 5.0 V Analog Supply (5%). Analog Input--True. Analog Input--Complement.
OUTPUT MODE
36 37 47, 54, 62, 75, 83 48, 53, 61, 67, 74, 82 63 64 66 68 69 70 71 72 73 76 77 78 79 80 81 84 85 100
CLK+ CLK- DRVDD DRGND DCO- DCO+ D0 (LSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 (MSB) OR DCS MODE
6
DFS
10
SENSE
11
VREF
12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, Exposed Heat Sink 13
AGND
REFT
14
REFB
19, 28 to 31, 39 to 40 21 22
AVDD2 VIN+ VIN-
Rev. 0 | Page 13 of 40
AD9444 EQUIVALENT CIRCUITS
AVDD2
DRVDD
VIN+
AVDD2
2.5pF
1k
DX
3.5V
05089-009
X1 1k
SHA
AVDD2
Figure 9. Equivalent CMOS Digital Output Circuit
05089-006
VIN- 2.5pF
VDD
Figure 6. Equivalent Analog Input Circuit
DRVDD DRVDD
DCS MODE, OUTPUT MODE, DFS 30k
05089-010
1.2V LVDSBIAS 3.74k
K
ILVDSOUT
05089-007
Figure 10. Equivalent Digital Input Circuit, DFS, DCS MODE, OUTPUT MODE
AVDD2
Figure 7. Equivalent LVDS BIAS Circuit
DRVDD
12k CLK+ 150 10k
12k CLK- 150 10k
V DX- V
V DX+ V
05089-008
Figure 8. Equivalent LVDS Digital Output Circuit
Figure 11. Equivalent Sample Clock Input Circuit
Rev. 0 | Page 14 of 40
05089-011
AD9444 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 80 MSPS, LVDS mode, DCS enabled, TA = 25C, 2 V p-p differential input, AIN = -0.5 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.
0 80MSPS 10.1MHz @ -0.5dBFS SNR: 73.9dB ENOB: 12.0BITS SFDR: 97dBc 0 80MSPS 100.3MHz @ -0.5dBFS SNR: 72.3dB ENOB: 11.8BITS SFDR: 96dBc
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05089-012
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Figure 12. 64K Point Single-Tone FFT/80 MSPS/10.1 MHz Figure 15. 64K Point Single-Tone FFT/80 MSPS/100 MHz
0 80MSPS 30.3MHz @ -0.5dBFS SNR: 74.0dB ENOB: 12.1BITS SFDR: 95dBc 0 80MSPS 125MHz @ -0.5dBFS SNR: 71.2dB ENOB: 11.6BITS SFDR: 91dBc
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05089-013
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Figure 13. 64K Point Single-Tone FFT/80 MSPS/30.3 MHz
0 80MSPS 70.3MHz @ -0.5dBFS SNR: 73.3dB ENOB: 11.9BITS SFDR: 100dBc 0
Figure 16. 64K Point Single-Tone FFT/80 MSPS/125 MHz
-20
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80MSPS 151MHz @ -0.5dBFS SNR: 71.1dB ENOB: 11.5BITS SFDR: 87dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
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Figure 14. 64K Point Single-Tone FFT/80 MSPS/70 MHz
Rev. 0 | Page 15 of 40
Figure 17. 64K Point Single-Tone FFT/80 MSPS/151 MHz
05089-017
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05089-016
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05089-015
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AD9444
75 74 73 SNR dB @ +25C 72 71 SNR dB @ +85C SNR dB @ -40C
75 74 SNR dB @ -40C 73 72 71 SNR dB @ +25C SNR dB @ +85C
(dB)
(dB)
05089-018
70 69 68 67 66 65 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY (MHz) 180 200
70 69 68 67 66 0 20 40 60 80 100 120 140 160 180 200
05089-021
65
ANALOG INPUT FREQUENCY (MHz)
Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
105 SFDR dBc @ +85C SFDR dBc @ +25C 100 95 90 85 80 75 70 0 20 40 60 80 100 120 140 160 ANALOG INPUT FREQUENCY (MHz) 180 200 SFDR dBc @ -40C
Figure 21. SNR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
105 SFDR dBc @ +85C 100 SFDR dBc @ +25C 95 90 85 80 75 70
(dB)
(dB)
SFDR dBc @ -40C
05089-019
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180
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Figure 19. SFDR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
Figure 22. SFDR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
120 THIRD -dBFS 110 100 90 80 SFDR -dBFS
SECOND -dBFS
120 SECOND -dBFS 110 100 90 THIRD -dBFS
SECOND -dBc
80
THIRD -dBc SFDR -dBFS
SFDR -dBFS
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05089-020
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ANALOG INPUT AMPLITUDE (dBc)
Figure 20. Single-Tone SFDR/Second/Third vs. Analog Input Level, 80 MSPS, AIN = 30.3 MHz
Figure 23. Single-Tone SFDR/Second/Third vs. Analog Input Level 80 MSPS, AIN = 70.30 MHz
Rev. 0 | Page 16 of 40
05089-023
10 -100
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05089-022
AD9444
0 SFDR: 102dBFS -20
0 -10 90dBFS REFERENCE LINE -20 -30 SFDR (dBc)
AMPLITUDE (dBFS)
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05089-024
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Figure 24. 32K Point Two-Tone FFT 80 MSPS/9.8 MHz/10.8 MHz
0 -10 -20 -30 SFDR: -100dBFS
Figure 27. Two-Tone SFDR vs. Analog Input Level, AIN = 9.8 MHz/10.8 MHz
0 -10 90dBFS REFERENCE LINE -20 -30
SFDR AND IMD3 (dB)
AMPLITUDE (dBFS)
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05089-028
05089-029
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ANALOG INPUT LEVEL (dBFS)
Figure 25. 32K Point Two-Tone FFT 80 MSPS/69.3 MHz/70.3 MHz
Figure 28. Two-Tone SFDR vs. Analog Input Level, AIN = 69.3 MHz/70.3 MHz
100
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05089-026
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Figure 26. SFDR vs. Sample Rate, VIN = 10.3 MHz @ -0.5 dBFS
Figure 29. SFDR vs. Sample Rate, VIN = 70.3 MHz @ -0.5 dBFS
Rev. 0 | Page 17 of 40
05089-027
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WORST THIRD-ORDER IMD (dBFS)
AD9444
0 -10 -20 -30 61.44MSPS TOTAL INPUT SIGNAL POWER: -30dBFS
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05089-030
FREQUENCY
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8179
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8183 BIN
8184
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Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz
0 -10 -20 -30
210 190 250
Figure 33. Ground Input Histogram 80 MSPS, VIN+ = VIN-, 32K Samples
NPR: 63.1dB
230
AMPLITUDE (dBFS)
-40 -50 -60 -70 -80 -90
CURRENT (mA)
AVDD1 (3.3V) 170 150 130 110 90 DRVDD (3.3V) 70 AVDD2 (5.0V)
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Figure 31. NPR, 80 MSPS/18 MHz Notch
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Figure 34. ISUPPLY vs. Sample Rate, AIN = 10.3 MHz @ -0.5 dBFS
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05089-035
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VIN COMMON-MODE (V)
Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle, FSAMPLE = 80 MSPS, 10.3 MHz @ -0.5 dBFS
Figure 35. Single-Tone SNR/SFDR vs. VIN Common-Mode Voltage 80 MSPS/10.3 MHz
Rev. 0 | Page 18 of 40
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AD9444
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05089-036
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Figure 36. VREF vs. Temperature
1.00 0.75 0.50
Figure 38. Gain vs. Temperature
1.00 0.75 0.50
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INL ERROR (LSB)
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10240 12288 14336 16384
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OUTPUT CODE
OUTPUT CODE
Figure 37. DNL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
Figure 39. INL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
Rev. 0 | Page 19 of 40
05089-038
-0.5 -40
AD9444 THEORY OF OPERATION
The AD9444 architecture is optimized for high speed and ease of use. The analog inputs drive an integrated, high bandwidth, track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipeline ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are user selectable as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT MODE pin.
Internal Reference Trim
The internal reference voltage is trimmed during the production test to adjust the gain (analog input voltage range) of the AD9444. Therefore, there is little advantage to the user supplying an external voltage reference to the AD9444. The gain trim is performed with the AD9444's input range set to 2 V p-p nominal (SENSE connected to AGND). Because of this trim, and because the 2 V p-p analog input range provides maximum ac performance, there is little benefit to using analog input ranges < 2 V p-p. Users are cautioned that the differential nonlinearity of the ADC varies with the reference voltage. Configurations that use < 2 V p-p may exhibit missing codes and, therefore, degraded noise and distortion performance.
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 10F + 0.1F SELECT LOGIC SENSE 0.5V 0.1F +
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V voltage reference is built into the AD9444. The input range can be adjusted by varying the reference voltage applied to the AD9444, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are described in the next few sections.
Internal Reference Connection
A comparator within the AD9444 detects the potential at the SENSE pin and configures the reference into four possible states, which are summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 40), setting VREF to ~1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a ~0.5 V reference output. If a resistor divider is connected, as shown in Figure 41, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as
R2 VREF = 0.5 x 1 + R1 In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
10F
Figure 40. Internal Reference Configuration
VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF + 10F 0.1F R2 SENSE 0.1F +
10F
SELECT LOGIC
R1
0.5V
AD9444
Figure 41. Programmable Reference Configuration
Rev. 0 | Page 20 of 40
05089-042
05089-043
AD9444
AD9444
Table 9. Reference Configuration Summary
Selected Mode External Reference Internal Fixed Reference Programmable Reference
Internal Fixed Reference
SENSE Voltage AVDD VREF 0.2 V to VREF
AGND to 0.2 V
Resulting VREF (V) N/A 0.5
R2 0.5 x 1 + (See Figure 41) R1
Resulting Differential Span (V p-p) 2 x External Reference 1.0 2 x VREF
2.0
1.0
External Reference Operation
The AD9444's internal reference is trimmed to enhance the gain accuracy of the ADC. An external reference may be more stable over temperature, but the gain of the ADC is not likely to be improved. Figure 36 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7 k load. The internal buffer still generates the positive and negative full-scale references, REFT and REFB, for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V.
VIN+
1Vp-p
3.5V
VIN-
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
05089-045
Figure 42. Differential Analog Input Range for VREF = 1 V
Analog Inputs
As with most new high speed, high dynamic range ADCs, the analog input to the AD9444 is differential. Differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. Most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. There are also benefits at the PCB level. First, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion of the AD9444 cannot be realized with a single-ended analog input, so such configurations are discouraged. Contact ADI for recommendations of other 14-bit ADCs that support single-ended analog input configurations. With the 1 V reference (nominal value, see the Internal Reference Trim section), the differential input range of the AD9444's analog input is nominally 2 V p-p or 1 V p-p on each input (VIN+ or VIN-).
The AD9444 analog input voltage range is offset from ground by 3.5 V. Each analog input connects through a 1 k resistor to the 3.5 V bias voltage and to the input of a differential buffer. The internal bias network on the input properly biases the buffer for maximum linearity and range (see the Equivalent Circuits section). Therefore, the analog source driving the AD9444 should be ac-coupled to the input pins. The recommended method for driving the analog input of the AD9444 is to use an RF transformer to convert single-ended signals to differential (see Figure 44). Series resistors between the output of the transformer and the AD9444 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. The series resistors, along with the 1 k resisters connected to the internal 3.5 V bias, must be considered in impedance matching the transformers input. For example, if RT were set to 51 and RS were set to 33 , along with a 1:1 impedance ratio transformer, the input would match a 50 source with a full-scale drive of 10.0 dBm. The 50 impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 47 and Figure 59).
ANALOG INPUT SIGNAL RT ADT1-1WT RS AIN
RS
0.1F
AD9444
05089-046
AIN
Figure 43. Transformer-Coupled Analog Input Circuit
Rev. 0 | Page 21 of 40
AD9444
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. For that reason, considerable care was taken in the design of the clock inputs of the AD9444, and the user is advised to give careful thought to the clock source. Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9444 contains a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. As shown in Figure 32, noise and distortion performance are nearly flat for a 30% to 70% duty cycle with the DCS enabled. The DCS circuit locks to the rising edge of CLK+ and optimizes timing internally. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 30 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically, which requires a wait time of 1.5 s to 5 s after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the time period the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependant on the duty cycle of the input clock signal. In such an application, it may appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the duty cycle stabilizer, and logic high (AVDD1 = 3.3 V) disables the controller. The AD9444 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of performance. Maintaining 14-bit accuracy places a premium on the encode clock phase noise. SNR performance can easily degrade by 3 dB to 4 dB with 70 MHz analog input signals when using a high jitter clock source. (See AN-501, Aperture Uncertainty and ADC System Performance, for complete details.) For optimum performance, the AD9444 must be clocked differentially. The sample clock inputs are internally biased to ~2.2 V, and the input signal is usually ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. Figure 44 shows one preferred method for clocking the AD9444. The clock source (low jitter) is converted from single-ended-todifferential using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9444 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9444 and limits the noise presented to the sample clock inputs. If a low jitter clock is available, another option is to ac couple a differential ECL/PECL signal to the encode input pins, as shown in Figure 46.
CLOCK SOURCE ADT1-1WT CLK+
0.1F
AD9444
HSMS2812 DIODES
05089-047
CLK-
Figure 44. Crystal Clock Oscillator, Differential Encode
VT
0.1F
ENCODE ECL/ PECL 0.1F
AD9444
ENCODE
05089-048
VT
Figure 45. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) and rms amplitude due only to aperture jitter (tJ) can be calculated using the following equation.
SNR = 20 log[2fINPUT x tJ]
In the equation, the rms aperture jitter represents the root-mean square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, see Figure 46. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9444. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
Rev. 0 | Page 22 of 40
AD9444
75 0.2ps 70
65 0.5ps
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50
tion resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor as close to the receiver as possible. It is recommended to keep the trace length less than 1 inch to 2 inches and to keep differential output trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic performance, the AD9444 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. CMOS outputs are available when OUTPUT MODE is CMOS logic low (or AGND for convenience). In this mode, the output data bits are singleended CMOS, DX, as is the overrange output, OR. The output clock is provided as a differential CMOS signal, DCO+/DCO-. Lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the ADC. The capacitive load to the CMOS outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 ) to minimize switching transients caused by the capacitive loading.
05089-049
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40 1 10 100 INPUT FREQUENCY (MHz) 1000
Figure 46. SNR vs. Input Frequency and Jitter
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of linear dc supplies is highly recommended. Switching supplies tend to have radiated components that may be received by the AD9444. Each of the power supply pins should be decoupled as closely to the package as possible using 0.1 F chip capacitors. The AD9444 has separate digital and analog power supply pins. The analog supplies are denoted AVDD1 (3.3 V) and AVDD2 (5 V) and the digital supply pins are denoted DRVDD. Although the AVDD1 and DRVDD supplies may be tied together, best performance is achieved when the supplies are separate. This is because the fast digital output swings can couple switching current back into the analog supplies. Note that both AVDD1 and AVDD2 must be held within 5% of the specified voltage. The DRVDD supply of the AD9444 is a dedicated supply for the digital outputs, in either LVDS or CMOS output modes. When in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply may be connected from 2.5 V to 3.6 V to be compatible with the receiving logic.
TIMING
The AD9444 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9444 determines the coding format of the output data. This pin is 3.3 V CMOS compatible, with logic high (or AVDD1, 3.3 V) selecting twos complement, and DFS logic low (AGND) selecting offset binary format. Table 10 summarizes the output coding.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide LVDS-compatible output levels via Pin 5 (OUTPUT MODE). LVDS outputs are available when OUTPUT MODE is CMOS logic high (or AVDD1 for convenience) and a 3.74 k RSET resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic performance, including both SFDR and SNR, is maximized when the AD9444 is used in LVDS mode, and designers are encouraged to take advantage of this mode. The AD9444 outputs include complimentary LVDS outputs for each data bit (DX+/DX-), the overrange output (OR+/OR-), and the output data clock output (DCO+/DCO-). The RSET resistor current is ratioed on-chip, setting the output current at each output equal to a nominal 3.5 mA (11 x I RSET ). A 100 differential termina-
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well as the pinout of the digital outputs. This pin is a CMOS compatible input. With OUTPUT MODE = 0 (AGND), the AD9444 outputs are CMOS-compatible and the pin assignment for the device is defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and the pin assignment for the device is defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS logic low (AGND) on DCS MODE enables the DCS, and logic high (AVDD1, 3.3 V) disables the controller.
Rev. 0 | Page 23 of 40
AD9444
Table 10. Digital Output Coding
Code 16383 8192 8191 0 VIN+ - VIN- Input Span = 2 V p-p (V) 1.000 0 -0.000122 -1.00 VIN+ - VIN- Input Span = 1 V p-p (V) 0.500 0 -0.000061 -0.5000 Digital Output Offset Binary (D9******D0) 11 1111 1111 1111 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000 Digital Output Twos Complement (D9******D0) 01 1111 1111 1111 00 0000 0000 0000 11 1111 1111 1111 10 0000 0000 0000
EVALUATION BOARD
Evaluation boards are offered to configure the AD9444 in either CMOS or LVDS mode. Each represents a recommended configuration for using the device over a wide range of sample rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. It is critical that signal sources with very low phase noise (< 1 ps rms jitter) be used to realize the ultimate performance of the converter. Proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. The evaluation boards are shipped with an ac to 6 V dc power supply. The evaluation boards include low dropout regulators to generate the various dc supplies required by the AD9444 and its support circuitry. Separate power supplies are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 47 to Figure 50 and Figure 59 to Figure 61).
Both the LVDS and CMOS versions of the evaluation board are compatible with the high speed ADC FIFO evaluation kit (part number HSC-ADC-EVALA-SC). The kit includes a high speed data capture board that provides a hardware solution for capturing up to 32Ksamples of high speed ADC output data in a FIFO memory chip (user upgradeable to 256K samples). Software is provided to enable the user to download the captured data to a PC via the USB port. This software also includes a behavioral model of the AD9444 and many other high speed ADCs. Behavioral modeling of the AD9444 is also available at www.analog.com/ADIsimADC. The ADIsimADCTM software supports virtual ADC evaluation using ADI proprietary behavioral modeling technology. This allows rapid comparison between the AD9444 and other high speed ADCs, with or without hardware evaluation boards. The AD9444 LVDS evaluation board includes an on-board, LVDS-to-CMOS translator, but the user may choose to remove the translator and terminations to access the LVDS outputs directly. The CMOS evaluation board includes a buffer for the output data and the DCO output clock of the AD9444.
Rev. 0 | Page 24 of 40
OPTIONAL ENCODE CIRCUITS
GND GND 50 R7 + C44 10F C93 0.1F P5 ENC 3 GND GND 8 7 6 5 4 3 2 1 R39 XX XTALINPUT J5 T3 ADT1-1WT CR2
1
ENCODE
VXTAL C92 0.1F GND
E47
5V
VXTAL
E52
E46 C36 0.1F
VCC
GND
GND U6 ECLOSC NC 5
3 4
GND GND 0.1F 1 2 GND ENCB GND PRI SEC C26 0.1F J1 ENCODE 50 R8 GND R37 XX
6 2
C42
R36 XX VXTAL 8 XTALOUTB 1 XTALOUT GND R12 VCC 1k R9 GND 1k GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
5V
VDL
VCC
DRVDD
VXTAL OUT ~OUT VXTAL R20 XX R27 XX GND R40 XX XTALINPUTB VXTAL E38 GND E40 XTALINPUT XTALOUTB XTALOUT 6 5 4 VCC E39 D11_C/D7_YN D11_T/D8_YN D12_C/D9_YN D12_T/D10_YN D13_C/D11_YN D13_T/D12_YN GND DRVDD DOR_C/D13_YN DOR_T/DOR_YN GND VCC GND VCC VCC VCC VCC VCC VCC VCC GND GND R38 XX
14
VCC
GND
7
VEE
GND
XTALINPUTB
R17 XX
FOR VECTRON XTAL
H4 MTHOLE6
H1 MTHOLE6
H2 MTHOLE6
H3 MTHOLE6
JN00158
LVDS EVALUATION BOARD SCHEMATICS
FOR VF XTAL R18 XX
GND
1 E/D 2 3 NC GND
VCC OUTPUTB OUTPUT
R19 XX EPAD
U2
GND
D11- D11+ D12- D12+ D13- D13+ (MSB) DRGND DRVDD OR- OR+ AGND AVDD1 AGND AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AGND AGND AVDD1 AGND DCS MOD
R15 VCC 1k
DRVDD
VCC GND 1k R14
E3
E1
Figure 47. LVDS Mode Evaluation Board Schematic
C86 GND VCC E25 E27 GND GND C3 0.1F 0.1F E26 GND VCC VCC E41 E24
Rev. 0 | Page 25 of 40
R1 3.8k R3 EXTREF GND C39 + C2 0.1F C51 10F R2 GND C9 0.1F 10F GND GND T5 ADT1-1WT TOUT R28 33 GND C12 0.1F R4 36 C13 20pF R13 xx R6 36 C91 0.1F TOUTB C5 TINB E15 0.1F NC
3 4 1 5 6 2
GND
E2
GND D10_T/D6_YN D10_C/D5_YN D9_T/D4_YN D9_C/D3_YN D8_T/D2_YN D8_C/D1_YN GND
E20
AD9444
U1 PIN DEFINITIONS LVDS/CMOS
3.8k
EXTREF
C24 0.1F GND VCC VCC VCC 5V GND
3.8k GND VCC VCC OPTIONAL
GND
D7_T/D0_YN D7_CN DRN DRBN DRVDD GND
GND
D2+ D2- DRGND DRVDD D1+ D1- D0+ (LSB) D0- AVDD1 AVDD1 AVDD2 AVDD2 AVDD1 CLK- CLK+ AVDD1 AVDD1 C1 AGND AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1
GND R5 J4 xx
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVDD1 DNC DNC DNC OUTPUT MODE DFS LVDSBIAS/DNC AVDD1 AVDD1 SENSE VREF AGND REFT REFB AGND AVDD1 AVDD1 AVDD1 AVDD2 AGND VIN+ VIN- AGND AVDD1 AVDD1
DRVDD DRGND D10+ D10- D9+ D9- D8+ D8- DRGND D7+ D7- DCO+ DCO- DRVDD DRGND D6+ D6- D5+ D5- D4+ D4- DRVDD DRGND D3+ D3- 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D6_TN D6_CN D5_TN D5_CN D4_TN D4_CN DRVDD GND D3_TN D3_CN
L1
GND
ANALOG
VCC VCC
GND 33 R35
VCC
VCC ENCB ENC VCC VCC
D2_TN D2_CN GND DRVDD D1_TN D1_CN D0_TN D0_CN VCC
GND C40 0.1F
5V
5V
GND
AD9444
05089-050
AD9444
POWER OPTIONS
ADP3338
U4
GND
ADP3338
U15 P4 GND
VDL VCC
GND
VDL
1 2 3
1 2 3
GND
2
VCC
2 3
4
OUT
OUT1 IN
4
OUT
OUT1 IN
3
VIN
VIN
1
+ + C57 10F
GND
C1 10F + C87 10F
+
C6 10F
+
C33 10F
GND
GND
ADP3338
U3
GND
GND
ADP3338
U14 1 2 3 1 2 3
GND
3.3V GND
DRVDD
5V
DRVDD
GND
5V
OUT
OUT1 IN
OUT
OUT1 IN
5V
4
4
+ + C88 10F
GND
VIN
C34 10F + C89 10F
+
C4 10F
GND
VIN
GND
Figure 48. LVDS Mode Evaluation Board Schematic (Continued)
VCC + GND VCC C10 XX GND C11 XX C14 XX C17 XX C16 XX C15 XX C31 XX C37 XX C38 XX C29 XX C19 XX C18 XX C90 XX C64 10F C43 0.1F C35 0.1F C32 0.1F C30 0.1F C28 0.1F C27 0.1F C48 0.1F C50 0.1F C60 0.1F C61 0.1F C46 0.1F C75 0.1F P19 GND
DRVDD + GND C65 10F C47 0.1F C23 0.1F C22 0.1F C21 0.1F C20 0.1F
DRVDD C69 XX GND C70 XX C45 XX C49 XX C59 XX
5V + GND C56 10F C85 0.1F C53 0.1F C52 0.1F C58 0.1F
5V C71 XX GND C72 XX C73 XX C62 XX
EXTREF
05089-052
+ GND
C55 10F
Figure 49. LVDS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 26 of 40
05089-051
GND
GND
VIN
1
GND
3.3V
3.3V
PJ-102A
AD9444
U7 SN75LVDS386 DOR_T/DOR_YN DOR_C/D13_YN D13_T/D12_YN D13_C/D11_YN D12_T/D10_YN D12_C/D9_YN D11_T/D8_YN D11_C/D7_YN D10_T/D6_YN D10_C/D5_YN D9_T/D4_YN D9_C/D3_YN D8_T/D2_YN D8_C/D1_YN D7_T/D0_YN D7_CN DRN DRBN D6_TN D6_CN D5_TN D5_CN D4_TN D4_CN D3_TN D3_CN D2_TN D2_CN D1_TN D1_CN D0_TN D0_CN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A1A A1B A2A A2B A3A A3B A4A A4B B1A B1B B2A B2B B3A B3B B4A B4B C1A C1B C2A C2B C3A C3B C4A C4B D1A D1B D2A D2B D3A D3B D4A D4B GND VCC1 VCC2 GND1 ENA A1Y A2Y A3Y A4Y ENB B1Y B2Y B3Y B4Y GND2 VCC3 VCC4 GND3 C1Y C2Y C3Y C4Y ENC D1Y D2Y D3Y D4Y END GND4 VCC5 VCC6 GND5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND VDL VDL GND VDL RZ5 220 RSO16ISO 1 2 3 4 VDL 5 6 7 GND VDL VDL GND DRP 8 R1 R2 R3 R4 R5 R6 R7 R8 16 15 14 13 12 11 10 9 ORO D13O D12O D11O D10O D9O D8O D7O
P6 C40MS GND 39 37 GND DOR_C/D13_YN D13_C/D11_YN D12_C/D9_YN D11_C/D7_YN D10_C/D5_YN D9_C/D3_YN D8_C/D1_YN D7_CN DRBN D6_CN D5_CN D4_CN D3_CN D2_CN D1_CN D0_CN GND 35 33 31 29 27 P39 P37 P35 P33 P31 P29 P27 P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND DOR_T/DOR_YN D13_T/D12_YN D12_T/D10_YN D11_T/D8_YN D10_T/D6_YN D9_T/D4_YN D8_T/D2_YN D7_T/D0_YN DRN D6_TN D5_TN D4_TN D3_TN D2_TN D1_TN D0_TN GND GND
25 P25 23 P23 21 P21 19 P19 17 P17 15 P15 13 P13 11 P11 9 P9 7 P7 5 P5 3 P3 1 P1
220 RSO16ISO 1 2 R1 R2 R3 R4 R5 R6 R7 R8 RZ4 16 15 14 13 12 11 10 9 D6O D5O D4O D3O D2O D1O D0O
VDL
3 4 5
VDL GND VDL VDL GND
6 7 8
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 GND 2
P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2
P39 39 P37 37 P35 35 P33 33 P31 31 P29 29 P27 27 P25 25 P23 23 P21 21 P19 19 P17 17 P15 15 P13 13 P11 11 P9 9 P7 7 P5 5 P3 3 P1 1
GND DRO GND D13O D12O D11O D10O D9O D8O D7O D6O D5O VDL D4O D3O D2O D1O D0O ORO
05089-053
74VCX86 1 1A 2 1B GND 00 XORN E43 E32 GND E34 R53 GND 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B VDL 3Y 4Y 3 1Y 2Y 6 8 00
DRO
11 R52 14 PWR 7 GND VDL GND
U10 + GND C76 10F C97 0.1F C82 0.1F C80 0.1F 81 0.1F
GND
P3 C40MS
Figure 50. LVDS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 27 of 40
AD9444
05089-057
Figure 51. LVDS Mode Evaluation Board Layout, Primary Side
Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2
05089-058
Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side
Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1
05089-059
Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1
Rev. 0 | Page 28 of 40
Figure 56. LVDS Mode Evaluation Board Layout, Power Plane 2
05089-062
05089-061
05089-060
AD9444
05089-063
Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen
Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen
Rev. 0 | Page 29 of 40
05089-064
AD9444
LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 11.
Item 1 2 Qty. 1 16 REFDES AD9444PCB C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64, C65, C76, C87 to C89 C2, C3, C5, C9, C12, C20 to C24, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C80 to C82, C85, C86, C91 to C93, C97 C51 CR2 E1 to E3, E24, to E27, E32, E34, E38, E39, E40, E41, E43, E46, E47, E52 J1, J4 L1 P3 P4 R3 R4, R6 R8 R9, R12, R14, R15 R28, R35 R39, R52, R53 RZ4, RZ5 T3, T5 U1 U3, U4, U15 U14 U6 U7 U10 U6 Description PCB, AD9444 LVDS Engineering Evaluation Board Capacitors, Tantalum, SMT BCAPTAJC, 10 F, 16 V, 10% Manufacturer PCSM KEMET MFG_PART_NO AD9444LVDSCUSTREVC T491C106K016AS
3
38
Capacitors, 0.1 F 10 V Ceramic X5R 0402
Panasonic
ECJ-0EB1A104K
4 5 6
1 1 17
Capacitor, Ceramic 10 F 6.3 V X5R 0805 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA 40-Pin Breakable Header
KEMET Panasonic 3M
C0805C106K9PACTU MA716-(TX) 2340-611TN
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2 1 1 1 1 2 1 4 2 3 2 2 1 3 1 1 1 1 4
Connector, Gold, Male, Coaxial, SMA, Vertical 10 nH Inductor Header, 40-Pin, Male, 40-Pin Right Angle Power Jack Resistor, 3.6 k 1/16 W 1% 0402 SMD Resistor, 36 1/16 W 5% 0402 SMD Resistor, 49.9 1/16 W 1% 0402 SMD Resistor, 1.00 k 1/16 W 1% 0402 SMD Resistor, 33 1/16 W 5% 0402 SMD Resistor, 0 1/16 W 5% 0402 SMD 22 Resistor Array, 16 Term Transformer, ADT1-1WT, CD542, ADT1-1WT 14-Bit, 80 MSPS ADC 3.3 V Voltage Regulator 5 V Voltage Regulator Clock Oscillator, 80 MHz LVDS-to-CMOS Translator with 100 Term 2 Input XOR Gate Pin Sockets, Closed End
Johnston Comp. Coilcraft Samtec Swithcraft Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic CTS Corp. Mini-Circuits ADI ADI ADI CTS Reeves Texas Instruments Fairchild AMP
142-0701-201 0603CJ-10NXGBU TSW-120-08-T-D-RA RAPC722 ERJ-2GEJ362X ERJ-2GEJ360X ERJ-2RKF49R9X ERJ-2RKF1001X ERJ-2GEJ330X ERJ-2GE0R00X 742163220JTR ADT1-1WT AD9444BSVZ-80 ADP3338-3.3 V ADP3338-5.0 V MX045-80 SN75LVDT386DGG 74VCX86M 5-330808-3
Rev. 0 | Page 30 of 40
AD9444
Item 26 Qty. 24 REFDES C10, C11, C13, to C19, C29, C31, C36 to C38, C45, C49, C59, C62, C69, C70 to C73, C901 J51 P5, P61 R1, R2, R5, R7, R131 R17 to R20, R27, R36 to R38, R401 U21 Description Capacitors, Select 10 V Ceramic X5R 0402 Manufacturer Panasonic MFG_PART_NO
27 28 29 30
1 2 1 1
Connector, Gold, Male, Coaxial, SMA, Vertical Power Connectors Resistors, Select 1/16 W 1% 0402 SMD Resistors, Select 1/16 W 1% 0402 SMD
Johnston Comp. Weiland Panasonic Panasonic
142-0701-201
31
5
XO Select
Vectron
1
Parts not placed.
Rev. 0 | Page 31 of 40
GND GND 50 R7 GND
ENCODE
AD9444
OPTIONAL ENCODE CIRCUITS
R39 XX P5 8 7 6 5 4 3 2 1 XTALINPUT ENC 3 + C44 10F GND GND GND GND T3 ADT1-1WT CR2
1
VXTAL C93 0.1F C92 0.1F C36 0.1F H1 MTHOLE6 H2 MTHOLE6 H3 MTHOLE6 H4 MTHOLE6 GND 5V VCC GND J1
3 4 6 2
E47
5V
VXTAL C42 0.1F 1 2 GND ENCB
E52
C96 0.1F
J5
E46 DRVDD NC 5 PRI SEC
VCC
VDL
R36 XX
U6 ECLOSC C26 0.1F VXTAL 50 R8 GND GND R37 XX 8 XTALOUTB 1 XTALOUT GND XTALINPUTB VXTAL VCC 1k R12 1k GND 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 GND R27 XX R20 XX GND R40 XX XTALINPUTB VCC E39 E38 GND E40 6 5 4 VXTAL XTALINPUT XTALOUTB XTALOUT D11C/D7YN D11T/D8YN D12C/D9YN D12T/D10YN D13C/D11YN D13T/D12YN GND DRVDD DORC/D13Y DORT/DORY GND VCC GND VCC VCC VCC VCC VCC VCC VCC GND GND R38 XX R9 OUT ~OUT
VXTAL
14
VCC
GND
7
VEE
GND
R17 XX
FOR VECTRON XTAL
JN00158
CMOS EVALUATION BOARD SCHEMATICS
FOR VF XTAL R18 XX U2 EPAD
GND
1 E/D 2 3 NC GND VCC OUTPUTB OUTPUT
R19 XX
D7 D8 D9 D10 D11 D12 DRGND DRVDD (MSB) D13 OR AGND DRVDD AGND AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 AGND AGND AVDD1 AGND DCS MODE
GND
R21 VCC 1k
DRVDD
VCC R15 GND 1k
E3
E1
Figure 59. CMOS Mode Evaluation Board Schematic
GND VCC E41 E24 GND GND C3 0.1F E25 E27 R1 E26 VCC VCC
Rev. 0 | Page 32 of 40
AD9444
U1 PIN DEFINITIONS LVDS/CMOS EXTREF GND C39 + R2 C78 0.1F C51 10F GND C9 0.1F 10F GND VCC VCC VCC 5V GND R28 33 GND T5 ADT1-1WT TOUT NC
3 4 1 5 6 2
GND
E2
GND D10T/D6YN D10C/D5YN D9T/D4Y D9C/D3Y D8T/D2Y D8C/D1Y GND D7T/D0Y COUT COUTB DRVDD GND
EXTERNAL REFERENCE INPUT E20 EXTREF
3.8k R3 C2 0.1F GND CT GND R4 36 R13 xx R6 36 GND 33 R35 C91 0.1F
3.8k
3.8k
GND
GND
GND PRI TOUTB E15 C12 SEC 0.1F C13 20pF
DNC DNC DRGND DRVDD DNC DNC DNC DNC AVDD1 AVDD1 AVDD2 AVDD2 AVDD1 CLK- CLK+ AVDD1 AVDD1 C1 AGND AVDD2 AVDD2 AVDD2 AVDD2 AVDD1 AVDD1
J4 OPTIONAL
R5 xx
100
GND VCC VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVDD1 DNC DNC DNC OUTPUT MODE DFS LVDSBIAS AVDD1 AVDD1 SENSE VREF AGND REFT REFB AGND AVDD1 AVDD1 AVDD1 AVDD2 AGND VIN+ VIN- AGND AVDD1 AVDD1
DRVDD DRGND D6 D5 D4 D3 D2 D1 DRGND D0 (LSB) DNC DCO+ DCO- DRVDD DRGND DNC DNC DNC DNC DNC DNC DRVDD DRGND DNC DNC 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DRVDD GND
GND
L110NH C5 TINB 0.1F ANALOG
VCC VCC 5V
VCC
VCC
VCC ENCB ENC VCC VCC 5V GND
GND DRVDD
GND C40 0.1F
05089-054
AD9444
ADP3338
U8
ADP3338
U15 P4
GND
GND
GND
1 2 3
GND
1 2 3
2
2 3
4
VCC
VDL
OUT
OUT1 IN
4
OUT
OUT1 IN
VCC
VDL
3
VIN
VIN
1
+ +
C1 10F
+
+
C6 10F
+
C33 10F
C57 10F
C87 10F
GND
GND
GND
ADP3338
U3
GND
ADP3338
U14
GND
DRVDD
OUT
5V
OUT1 IN
OUT
OUT1 IN
+ +
C34 10F
+
VIN
+
C4 10F
C88 10F
C89 10F
GND
GND
VIN
3
3
5V
4
2
DRVDD
GND
1
GND 4
1 2
GND
3.3V
5V
GND
GND
Figure 60. CMOS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 33 of 40
GND
05089-055
VIN
1
GND
3.3V
3.3V
PJ-102A
AD9444
40 RZ1 220 RSO16ISO DORT/DORY DORC/D13Y D13T/D12Y D13C/D11Y D12T/D10Y D12C/D9Y D11T/D8Y D11C/D7Y 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 16 15 14 13 12 11 10 9 GND VDL GND XOR2IN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 U5 SN74LVCH16373A Q = OUTPUT LE2 D = INPUT OE2 2Q8 2D8 2Q7 2D7 GND GND 2Q6 2D6 2Q5 2D5 VCC VCC 2Q4 2D4 2Q3 2D3 GND GND 2Q2 2D2 2Q1 2D1 1Q8 1D8 1Q7 1D7 GND GND 1Q6 1D6 1Q5 1D5 VCC VCC 1Q4 1D4 1Q3 1D3 GND GND 1D2 1Q2 1Q1 1D1 LE1 OE1 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND 220 RZ5 RSO16ISO 1 2 3 GND 4 5 VDL 6 7 GND 8 R1 R2 R3 R4 R5 R6 R7 R8 16 15 14 13 12 11 10 9 ORM D13M D12M D11M D10M D9M D8M D7M 38 36 34 32 30 28 26 24 22 20 18 16 D6M D5M D4M D3M D2M D1M D0M GND 14 12 10 8 6 4 2 P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 P39 39 P37 37 P35 35 P33 33 P31 31 P29 29 P27 27 P25 25 P23 23 P21 21 P19 19 P17 17 P15 15 P13 13 P11 11 P9 9 P7 7 P5 5 P3 3 P1 1 GND GND DRM GND D13M D12M D11M D10M D9M D8M D7M D6M D5M D4M D3M D2M D1M D0M ORM
RZ2 220 RSO16ISO D10T/D6Y D10C/D5Y D9T/D4Y D9C/D3Y D8T/D2Y D8C/D1Y D7T/D0Y 1 2 3 4 5 6 7 8 R1 R2 R3 R4 R5 R6 R7 R8 RZ4 16 15 14 13 12 11 10 9 XOR2IN GND VDL GND
RZ5 220 RSO16ISO GND 1 2 VDL 3 4 GND 5 6 GND 7 8 R1 R2 R3 R4 R5 R6 R7 R8 RZ4 16 15 14 13 12 11 10 9
P3 C40MS
NOT PLACED 00 COUTB R50 00 COUT VDL E42 GND E45 GND R16 E49 XORZIN 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B VDL E31 GND E30 E32 GATE2 12 4A 13 4B 3Y 4Y U4 74VCX86 3 1Y 2Y 6 8 11 14 PWR 7 GND 00 R42 VDL GND DRM 00 R41 GATE 00 R14 DRM
U10 VDL
05089-056
+ GND
C66 10F
C25 0.1F
C41 0.1F
C24 0.1F
C68 0.1F
C67 0.1F
63 0.01F
Figure 61. CMOS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 34 of 40
AD9444
05089-065
Figure 62. CMOS Mode Evaluation Board Layout, Primary Side
Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2
05089-066
Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side
Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1
05089-067
Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1
Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2
Rev. 0 | Page 35 of 40
05089-070
05089-069
05089-068
AD9444
05089-071
Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen
Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen
Rev. 0 | Page 36 of 40
05089-072
AD9444
CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 12.
Item 1 2 Qty. 1 16 REFDES AD9444PCB C1, C4, C6, C33, C34, C39, C44, C55 to C57, C64 to C66, C87 to C89 Description PCB, AD9444 LVDS Evaluation Board Capacitors, Tantalum, SMT BCAPTAJC, 10 F, 16 V, 10% Manufacturer PCSM KEMET MFG_PART_NO AD9444LVDSCUSTREVC T491C106K016AS
3
32
C2, C3, C5, C9, C12, C20 to C23, C26 to C28, C30, C32, C35, C40, C42, C43, C46 to C48, C50, C52, C53, C58, C60, C61, C75, C78, C85, C91, C92
Capacitors, 0.1 F 10 V Ceramic X5R 0402
Panasonic
ECJ-0EB1A104K
4 5 6 7
5 1 1 20
C24, C25, C41, C67, C68 C51 CR2 E1 to E3, E24 to E27, E30 to E32, E38 to E42, E45 to E47, E49, E52
Capacitors, 0.1 F 16 V Ceramic X7R 0603 Capacitor, Ceramic 10 F 6.3 V X5R 0805 Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA 40-Pin Breakable Header
Panasonic KEMET Panasonic 3M
ECJ-1VB1C104K C0805C106K9PACTU MA716-(TX) 2340-611TN
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2 1 1 1 1 2 1 4 2 2 1 4 2 1 4 1 1 4
J1, J4 L1 P3 P4 R3 R4, R6 R8 R9, R12, R15, R21 R14, R50 R28, R35 R39 RZ1 to RZ3, RZ6 T3, T5 U1 U3, U8, U15 U14 U5 U6
Connector, Gold, Male, Coaxial, SMA, Vertical 10 nH O402 Inductor Header, 40-Pin, Male, 40-Pin Right Angle Power Jack Resistor, 3.6 k 1/16 W 1% 0402 SMD Resistors, 36 1/16 W 5% 0402 SMD Resistor, 49.9 1/16 W 1% 0402 SMD Resistors, 1.00 k 1/16 W 1% 0402 SMD Resistors, 0 1/10 W 5% 0603 SMD Resistors, 33 1/16 W 5% 0402 SMD Resistor, 0 1/16 W 5% 0402 SMD 220 Resistor Array, 16 Term Transformer, ADT1-1WT, CD542, ADT1-1WT 14-Bit, 80 MSPS ADC 3.3 V Voltage Regulator 5 V Voltage Regulator 16-Bit Flip Flop Pin Sockets, Closed End
Johnston Comp. Coilcraft Samtec Swithcraft Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic CTS Corp. Mini-Circuits ADI ADI ADI Fairchild AMP
142-0701-201 0402CS-10NX_B_ TSW-120-08-T-D-RA RAPC722 ERJ-2GEJ362X ERJ-2GEJ360X ERJ-2RKF49R9X ERJ-2RKF1001X ERJ-3GEY0R00V ERJ-2GEJ330X ERJ-2GE0R00X 742163221JTR ADT1-1WT AD9444BSVZ-80 ADP3338-3.3 V ADP3338-5.0 V 74LVTH162374 5-330808-3
Rev. 0 | Page 37 of 40
AD9444
Item 26 Qty. 26 REFDES C10, C11, C13, C14 to C19, C29, C31, C36 to C37, C38, C45, C49, C59, C62,C69, C70 to C73, C90, C93, C961 J51 R1,R2,R5,R7, R13, R17 to R20, R27, R36 to R401 R16, R41, R421 C631 U41 P5, P61 Description Capacitors, Select 10 V Ceramic X5R 0402 Manufacturer Panasonic MFG_PART_NO
27 28
1 15
Connector, Gold, Male, Coaxial, SMA, Vertical Resistors, Select 1/16 W 1% 0402 SMD
Johnston Comp. Panasonic
142-0701-201
29 30 31 32
3 1 1 2
Resistors, Select 1/16 W 5% 0603 SMD Capacitor, Select 10 V Ceramic X5R 0603 XOR 74VCX86D Power Connectors
Panasonic Panasonic Fairchild Weiland
74VCX86D
1
Parts not placed.
Rev. 0 | Page 38 of 40
AD9444 OUTLINE DIMENSIONS
0.75 0.60 0.45 SEATING PLANE 1.20 MAX
100 1
16.00 SQ 14.00 SQ
76 75 76 75 100 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE HEAT SINK 25 26 51 50 51 50 26 25
0.20 0.09 7 3.5 0
1.05 1.00 0.95
6.50 NOM
0.50 BSC
0.27 0.22 0.17
0.15 0.05
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD NOTES 1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED. 2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. 3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.
Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9444BSVZ-801 AD9444-CMOS/PCB AD9444-LVDS/PCB Temperature Range -40C to +85C Package Description 100-Lead TQFP_EP CMOS Mode Evaluation Board LVDS Mode Evaluation Board Package Outline SV-100-1
1
Z = Pb-free part.
Rev. 0 | Page 39 of 40
AD9444 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05089-0-10/04(0)
Rev. 0 | Page 40 of 40

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